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Advance Information
MC13181/D Rev. 0, 08/2002 Wireless Power Management Integrated Circuit
MC13181
(Scale 2:1)
Package Information Plastic Package Case 1307 (QFN-24) Ordering Information
Device MC13181R2 Marking 13180 Package QFN-24
The MC13181 Wireless Power Management Integrated Circuit (PMIC) is a monolithic IC designed for hand-held electronics products in conjunction with the Motorola Bluetooth chipset (the MC13180 Bluetooth Radio and MC71000 Bluetooth Protocol Controller) or stand-alone in other products. The MC13181 is ideal for devices operating from a 3.6 V single-cell Lithium-ion battery or other energy systems in the 2.85 to 6.5 V range. The IC features three independently enabled Low Drop Out (LDO) Linear Voltage Regulators for powering baseband, audio, RF/IF, and interface circuitry. A comparator with logic-enabled hysteresis and one scaled input is provided for use as a low-battery detector to protect against destructive battery discharge; it can alternately be used for general system interfacing. A supervisory circuit is integrated to provide a reset signal to the Protocol Controller indicating valid supply. An over-temperature shutdown function is integrated to protect against excessive power dissipation. A Shutdown input line is provided to allow for disabling of all active circuitry to minimize battery loading and to provide single line master disable. Logic inputs accept Vih levels from 1.5 V to VCC. Typical Applications * * * * * * Add-On Bluetooth Adaptor Cards for Cellular Phones Cellular Phones USB Dongle GPS or PDA Cordless Headsets Other portable devices requiring multiple independent regulators in one package
This document contains information on a pre-production product. Specifications and Pre-production information herein are subject to change without notice. (c) Motorola, Inc., 2002. All rights reserved.
Features * * Low-Battery Detector Three LDO Voltage Regulators: 2.65 V, 65 mA for RF/IF 1.85 V, 30 mA for Baseband 3.0/3.3 V, 60 mA for USB, Audio CODEC, or other circuitry Integrated Pass Device Independent Enable Lines Optimized for Low-Cost Bypass Capacitors Microprocessor Supervisor Circuit General Purpose Inverter, OR Gate and Comparator Maximum VCC Rated up to 7.0 V (6.5 V recommended) Voltage-Robust, Level Shifted Logic Inputs to VCC (6.5 V) Seamless Integration with Motorola's Bluetooth Chipset Thermal Shutdown
VCC
2
* * * * * *
1.265 V
Ref
Hys
2.65 EN 2.65 V 65 mA 1.85_EN 1.85 V 30 mA Select 3.0/3.3_EN 3.0/3.3 V 60 mA
LDO 2.65
LDO 1.85
LDO 3.0/3.3 Thermal Shutdown
Shutdown Reset Reset
Figure 1. Simplified Block Diagram
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Electrical Specifications
1 Electrical Specifications
Table 1. Maximum Ratings
Ratings Power Supply Input Voltage Voltage Input Output Voltage Output Short Circuit Duration Thermal Resistance, Junction to Ambient Storage Temperature Range Operating Junction Temperature Lead Soldering Temperature @ 260C
NOTE:
Symbol VI Vin Vout Rja Tstg TJ Tsolder
Value 0 to 7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 Infinite 115 -40 to 150 125 10
Unit V V V C/W C C sec
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Contact Description section.
Table 2. Maximum Package Power Dissipation
The power dissipation level at which the junction temperature reaches its maximum operating value, i.e., 125C. Characteristic Power Dissipation, in air Power Dissipation, 4-layer board Symbol Pd Pd Min Typ Max 345 1000 Unit mW mW
Table 3. Recommended Operating Conditions
Characteristic Supply Voltage Temperature Range Symbol VCC TA Min 2.85 -40 Typ Max 6.5 85 Unit V C
Table 4. Electrical Characteristics
(VCC = 3.6 V, Cin = 1.0 F, Cout = 1.0 F, TA = 25C for typical values, unless otherwise noted.) Characteristic LDO_1.85 Output Voltage in 1.85 V Mode Line Regulation (VCC2 = 2.85 V to 6.5 V, Iout = 15 mA) Load Regulation (Iout = 10 A to 30 mA) Vout REGline REGload 1.813 1.85 1.0 15 1.887 10 45 V mV mV Symbol Min Typ Max Unit
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Electrical Specifications Table 4. Electrical Characteristics (Continued)
(VCC = 3.6 V, Cin = 1.0 F, Cout = 1.0 F, TA = 25C for typical values, unless otherwise noted.) Characteristic Ripple Rejection (Ripple 0.5 Vpp, VCC = 2.95 V, Io = 15 mA) f = 1.0 kHz Output Noise Voltage @ Io = 20 mA (f = 10 kHz to 100 kHz) Short Circuit Current Limit (Vout = 0 V) Supply Current in ON mode (Iout = 0 mA) Output Capacitor ESR of Output Capacitor Output Voltage Transient Response (10% to 100% of Imax) Output Turn On Time from Enable to 90% of final value Output Voltage Temperature Coefficient Ton TC Symbol PSRR Min 40 Typ Max Unit dB Vrms mA A F % s ppm / C
Vn Ilim ISS Cout ESR
-
30
-
1 -
90 30 5.0 1.0
40 -
-
20 100
100 -
LDO_2.65 Output Voltage Dropout Voltage V VCC-Vout REGline REGload PSRR Vn Ilim ISS Cout ESR 60 41 34 30 Vrms mA A F W % s 2.60 2.65 1.0 2.70 V mV/ mA mV
Line Regulation (VCC1 = 2.85 V to 6.5 V, Iout = 32.5 mA) Load Regulation (Iout = 10 A to 65 mA) Ripple Rejection, (VCC Ripple = 0.5 Vpp, Io = 32.5 mA) f = 1.0 kHz f = 10 kHz f = 1 MHz Output Noise Voltage @ Io = 50 mA (f = 10 kHz to 100 kHz) Short Circuit Current Limit (Vout = 0 V) Supply Current in ON mode (Iout = 0 mA) Output Capacitor ESR of Output Capacitor Output Voltage Transient Response (10% to 100% of Imax) Output Turn On Time from Enable to 90% of final value
-
3.0
10
-
15
45
mV dB
1.0 -
200 100 4.0 1.0
125 -
Ton
-
20
100
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Electrical Specifications Table 4. Electrical Characteristics (Continued)
(VCC = 3.6 V, Cin = 1.0 F, Cout = 1.0 F, TA = 25C for typical values, unless otherwise noted.) Characteristic Output Voltage Temperature Coefficient Symbol TC Min Typ 100 Max Unit ppm / C
LDO_3.0/3.3 Output Voltage in 3.0 V Mode Select High Output Voltage in 3.3 V Mode Select Low Dropout Voltage Vout Vout VCC-Vout REGline REGload PSRR 40 Vn Ilim Iss 30 Vrms mA A F W % s ppm / C 3.0 3.234 3.06 3.3 1.0 3.12 3.366 V V mV/ mA mV mV dB
Line Regulation (VCC = 3.5 V to 6.5 V, Iout = 30 mA) Load Regulation (Iout = 10 A to 60 mA) Ripple Rejection, (Ripple 0.5 Vpp, VCC = Vout + 0.6 V, Io = 30 mA) f = 1.0 kHz Output Noise Voltage @ Io = 50 mA (f = 10 kHz to 100 kHz) Short Circuit Current Limit (Vout = 0 V) Supply Current in ON mode (VCC = Vout + 0.6 V, Iout = 0 mA) Output Capacitor ESR of Output Capacitor Output Voltage Transient Response (10% to 100% of Imax) Output Turn On Time from Enable to 90% of final value Output Voltage Temperature Coefficient
-
2.5 8.0
10 45
-
200 10
65
Cout ESR
1.0 -
4.0 1.0
-
Ton TC
-
50 100
100 -
RESETB Circuit with Programmable Delay ResetB Threshold ResetB Active Timeout period with Delay Cap = 5.6 nF with Delay Cap = 68 nF Output Voltage Low Output Voltage High VTH Treset 8.0 Vol Voh |Io| 0 14 170 VLDO_1.
85
1.65
1.70
1.75
V ms
300 0.1 V V
Output Current RESETB (source or sink)
1.0
-
-
mA
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Electrical Specifications Table 4. Electrical Characteristics (Continued)
(VCC = 3.6 V, Cin = 1.0 F, Cout = 1.0 F, TA = 25C for typical values, unless otherwise noted.) Characteristic Comparator with Programmable Hysteresis Input Offset Voltage Input Impedance (Vin + and Vin -) Input Voltage Range Vin + Voffset Rin -5.0 1600 5.0 mV k V Vin+ 1.0 VCC2 1V V 1.0 Vol Voh SR |Io| 1.0 100 200 mA mV 30 0 VLDO_1.85
Symbol
Min
Typ
Max
Unit
Input Voltage Range Vin - (scaling factor of approximately 0.44) Output Voltage Low Output Voltage High Slew Rate CL = 50 pF Positive Slope Negative Slope Output Current DETECT (source or sink) Hysteresis Voltage Pin HYS SELECT Low (hysteresis enabled) Voltage Reference (Cout = 470 nF Ceramic) VCC Operating Range Output Voltage Temperature Coefficient Line Regulation Output Capacitor Startup Time OR Gate VCC Operating Range Output Voltage Low Output Voltage High Inverter Gate Hysteresis Voltage Output Voltage Low
VinVCC2 0.1 -
V V V/s
VCC1 Vref TCVref VREF_LINE
2.2 1.250 -
1.265 0.022 0.08 470 1.0
6.5 1.278 -
V V mV/C mV/V nF ms
Tstartup
-
VCC2 Vol Voh
2.2 1.55
-
6.5 0.1 VCC2
V V V
Vol -
50 -
0.1
mV V
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Electrical Specifications Table 4. Electrical Characteristics (Continued)
(VCC = 3.6 V, Cin = 1.0 F, Cout = 1.0 F, TA = 25C for typical values, unless otherwise noted.) Characteristic Output Voltage High Symbol Voh Min Typ VLDO_1.
85
Max -
Unit V
Common Quiescent Current VCC1 (all LDO enables low) Quiescent Current VCC2 (all LDO enables low) Quiescent Current VCC (SHUTDOWN_B low) Input Voltage Low (enable, shutdown, Q1_B, Q2, hys sel, 3.0/3.3 select) Input Voltage High (enable, shutdown, Q1_B, Q2, hys sel, 3.0/3.3 select) Pull Down Resistor (enable, Q2, select) VCC Differential (VCC2 > VCC1) VCC Differential (VCC1 > VCC2) Icq1 Icq2 Icq sd Vil Vih Rpd VCC2-VCC1 VCC1-VCC2 0 30 7.0 1.8 42 13 0.15 A A A V
1.5
-
VCC2 0.3 VCC1
V
-
1.0 0 0
M V V
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Electrical Specifications
VOUT1.85 (1.85 V, 30 mA) (with optional connections for Low Battery detection)
(REFOUT) VIN+
(VCC2) VIN-
AGND2 DETECT HYSSEL
*1.0 F
24
LDO 2.65 VOUT2.65 (2.65 V, 65 mA) *1.0 F
23
22
21
VCC2
20
19
1
VOUT GND
EN
VOUT1.85 882 k
LDO_1.85
VIN EN VOUT GND
VOUT1.85
VIN 734 k 1M SHUTDOWN_B TSD_B
Globally Distributed REFOUT (1.265 V) REF
18
SHUTDOWN_B TSD_B
1.85_EN
2
*470 nF *0.1 F 1.0 F
VOUT GND
IREF EN VIN
17
SHUTDOWN_B SHUTDOWN_B 1M
2.65_EN
VCC1
3
Thermal Shutdown VCC2 REFOUT VOUT1.85 Threshold = 1.7 V TSD_B
VIN CAP GND RESET_B
16
SHUTDOWN_B
AGND1 SGND
4 5
Local Substrate Moat
VCC REF VOUT
15
RESET_B
SHUTDOWN_B TSD_B
RESET
VOUT1.85 Q1_B S_INV
14
VCC2 1M Q1_B VCC2
3.0/3.3_SEL
6
INV
13
OR 1M 1M
3.0/3.3_EN
GND V-SEL EN VOUT
VCC2
LDO_3.0/3.3
7
*1.0 F * Mount part close to IC VOUT3.0/3.3 (3.0/ 3.3 V, 60 mA) *1.0 F 1.0 F
8
User Defined
9
10
Q1_B
11
Q2
12
S_OR
VCC2
DELAY_CAP
Figure 2. Simplified Functional Diagram
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Pin Function Descriptions
2 Pin Function Descriptions
Table 5. Pin Function Description
Pin 1 Symbol/ Type VOUT2.65 Description VOUT2.65 Regulator Output, LDO_2.65, 2.65 V, 65 mA Output
Cext 1 162 k ESD
Equivalent Internal Circuit
Notes Bypass with low ESR 1.0 F tantalum capacitor [Note 1]
VCC1 Vref
152 k
2
REFOUT
REFOUT,1.265 V Reference Voltage Output,
VCC1 2.0 k
Bypass with low ESR 470 nF [Note 1]
Band Gap
1.0 k Cext 2 274 k
3
VCC1
VCC1, Positive Supply, Power Supply Input for Reference Generation and LDO_2.65
to VCC
3* * also pin 8
C bypass (2)
ESD
Bypass with a 0.1 F close to the part and a 1.0 F low ESR. Tie to ground
4
AGND1
AGND1 Ground, Analog Ground for Reference Generation and LDO_2.65
4
A ground 1
ESD
5
SGND
SGND Ground, Substrate for LDO_2.65 and Reference Generator
5
S ground
Tie to ground
ESD
6
S_INV
S_INV, Inverter Output
LDO_1.85
referenced to VLDO_1.85
6*
ESD
* also pins 15 & 22
NOTES: 1. All capacitors are assumed to be low ESR tantalum. De-rating factor on capacitance value is assumed to be -20% to 10% over all cases of tolerance and temperature. 2. Contact assignments are subject to change.
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Pin Function Descriptions Table 5. Pin Function Description (Continued)
Pin 7 Symbol/ Type VOUT3.0/3.3 Description VOUT3.0/3.3 Regulator, LDO_3.0/3.3, 60 mA Output
Cext 7 23 k ESD 160 k 3.0/3.3 select
Equivalent Internal Circuit
Notes Bypass with low ESR 1.0 F tantalum capacitor [Note 1]
VCC2 Vref
115 k
8
VCC2
VCC2, Positive Supply, Power Supply Input for non-VCC1 blocks
same as pin 3
Bypass with a 0.1 F close to the part and a 1.0 F low ESR.
Vref
9
DELAY_CAP
DELAY_CAP, Reset Delay Cap Input
Cdelay 9
500 nA ESD
10
Q1_B
Q1_B, Input to Inverter and Complementary Input to OR Gate
10*
VCC2 500 nA
can tolerate high to VCC
ESD * also pins 16 & 21
11
Q2
Q2, Input to OR Input
VCC2 500 nA 11*
1.0 M
can tolerate high to VCC
ESD * also pins 13, 14, 17 & 18
NOTES: 1. All capacitors are assumed to be low ESR tantalum. De-rating factor on capacitance value is assumed to be -20% to 10% over all cases of tolerance and temperature. 2. Contact assignments are subject to change.
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Pin Function Descriptions Table 5. Pin Function Description (Continued)
Pin 12 Symbol/ Type S_OR Description S_OR, OR Output Equivalent Internal Circuit Notes referenced to VCC2
12
13
3.0/3.3_EN
3.0/3.3_EN, LDO_3.0/ 3.3 Enable 3.0/3.3_SEL, Input logic control for 3.0 or 3.3 V from LDO_3.0/3.3 RESET_B, Reset PushPull Output SHUTDOWN_B, Single Pin Master Disable 2.65_EN, LDO_2.65 Enable 1.85_EN, LDO_1.85 Enable VOUT1.85 Regulator, LDO_1.85, 1.85 V, 30 mA Output,
same as pin 11
high = enable high = 3.0 V, low = 3.3 V referenced to VLDO_1.85 Low = IC Shutdown high = enable high = enable
VCC2 Vref
14
3.0/3.3_SEL
same as pin 11
15
RESET_B
same as pin 6
16
SHUTDOWN _B 2.65_EN
same as pin 10
17
same as pin 11
18
1.85_EN
same as pin 11
19
VOUT1.85
Cext
19 90 k ESD
Bypass with low ESR 1.0 F tantalum capacitor [Note 1]
200 k
20
AGND2
AGND2 Ground, Analog Ground HYSSEL, Input logic control for Comparator Hysteresis
Ground
Tie to ground Low = hysteresis enabled, High = hysteresis disabled referenced to VLDO_1.85
21
HYSSEL
same as pin 10
22
DETECT
DETECT, Comparator Push-Pull Output
same as pin 6
NOTES: 1. All capacitors are assumed to be low ESR tantalum. De-rating factor on capacitance value is assumed to be -20% to 10% over all cases of tolerance and temperature. 2. Contact assignments are subject to change.
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Pin Function Descriptions Table 5. Pin Function Description (Continued)
Pin 23 Symbol/ Type VINDescription VIN-, Inverting Input to Comparator through divider string VIN+, Non-inverting Input to Comparator Equivalent Internal Circuit Notes Typically, VIN- will be connected to VCC and VIN+ to the reference to detect low battery.
to VCC
23 882 k
24
VIN+
ESD en
717 k
Hys. 17 k
to ref
24
ESD
NOTES: 1. All capacitors are assumed to be low ESR tantalum. De-rating factor on capacitance value is assumed to be -20% to 10% over all cases of tolerance and temperature. 2. Contact assignments are subject to change.
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Circuit Features
3 Circuit Features
3.1 Low Drop Out Regulators (LDO)
All three regulators are designed for use with low-value, low-cost bypass capacitors. Low ESR tantalum capacitors are recommended (high performance ceramic capacitors with extremely low ESR, 1, should be avoided at regulator outputs to ensure stability, see Table 4 (Electrical Characteristics) for allowable ESR range for each regulator). The output capacitors should be 1.0 F minimum and should be mounted close to the IC. Better transient performance can be achieved with a larger output capacitor. In general turn-on and turn-off time will increase in proportion to the capacitor value. the regulators may not meet specified turn-on time with a larger capacitor.
Table 6. LDO Regulators
LDO LDO_1.85 LDO_2.65 LDO_3.0/3.3 LDO_3.0/3.3 Voltage (V) 1.85 2.65 3.0 3.3 Current (mA) 30 65 60 60 SEL high low Cout (F) 1.0 1.0 1.0 1.0
Additional filter capacitors should be placed across each VCC input. A 0.1 F ceramic close to the IC and a 1.0 F tantalum (placement is less critical) are recommended. All three regulators are designed for high Power Supply Rejection Ratio, low standby current, good line and load regulation, and fast turn on. The first regulator, LDO_1.85, supplies 1.85V. It is capable of a nominal output current of 30 mA. This regulator is ideal for powering low-voltage digital or baseband circuitry. The second regulator, LDO_2.65, supplies 2.65 V at up to 65 mA. This regulator is intended to supply power for RF/IF circuitry. This regulator is optimized for slightly better close-in PSRR performance, and derives its power from the VCC1 input pin. The input to the MC13180, which this LDC supplies current, requires at least 2.55 V. The additional voltage of LDO_2.65 allows for a series resistor, shunt capacitor filter into incorporate to further improve PSRR on that line. The resistor must be 0.220 minimum, and the capacitor 1.0 to 2.2 F. The maximum resistor value should be chosen so that maximum current will result in a voltage drop of 0.1 V or less. The third regulator, LDO_3.0/3.3, can be set to either 3.0 V out to 3.3 V out through a single select line. This output can source 60 mA. This regulator can be used to supply USB power or power an audio CODEC or some other peripheral as needed. If the input voltage drops below the overhead needed for regulation, the output of this regulator will track the input down to 2.7 V. The LDO_1.85 and LDO_3.0/3.3 regulators derive their power from the VCC2 input pin. This allows filtering to be tailored for the load circuitry, and to isolate the noisy digital (1.85 V) peripheral (3.0/3.3 V) from the RF (2.65 V) and reference of the IC. Each regulator has an independent, active-high enable line. This line can accept a "high" (to turn on the regulator) input of 1.5 V up to either VCC, and can be tied directly to VCC if the enable function is not to be used (shutdown will still function). If a given regulator is not needed in the application, the appropriate enable input can be tied low (<1.5 V) and the output capacitor eliminated. Care should be taken if the enable pin is to be driven from a processor powered by the corresponding regulator.
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Circuit Features
3.2 Reference Regulator
The Reference Regulator supplies a precise 1.265 V for use by the other on-chip regulators. To maintain spectral purity on the LDO regulators, this internal reference is not intended for external loading. A pin is provided for an off-chip 0.47 F capacitor for bypassing. The reference regulator derives its power from the VCC1 pin. Since the reference regulator supplies reference to the other regulators, power should not be applied to VCC2 if VCC1 is unpowered.
3.3 Shutdown
The active-low shutdown input disables all regulators and logic. In the shutdown state, the total IC current consumption is 2.0 A. Shutdown also disconnects the input resistor of the divider on the VIN- input to the comparator. As this would typically be connected to VCC for battery voltage detection. Shutting down MC13181 removes this approximately 5.0 A current. Care should be taken if this pin is to be driven from a processor operating on a voltage supplied by MC13181.
3.4 Reset Circuit
The RESET_B output goes high after a delay, based on the delay capacitor. It is initiated when VLDO_1.85 rises above the reset threshold of 1.70 V. When VLDO_1.85 falls below the reset threshold, RESET_B goes low with no delay. To calculate the value of the delay capacitor needed for a given delay, the formula C/I = dV/dT can be used. At the start of the delay, the capacitor is shorted nearly to 0 V, and then charged with a 500 nA current source until its voltage reaches the reference voltage, 1.265 V. T delay = C * V / I, simplifies to T delay (ms) ~= 2.53 x C (nF) or, C (nF) ~= T / 2.53 (T in ms) Note: The threshold voltage, resistance of the shorting FET and the current source will vary with temperature and VCC2, so the resulting delay will vary by 2:1 or more.
3.5 Comparator with Programmable Hysteresis
The MC13181 includes a general purpose comparator. The IC's VIN- input incorporates internal resistors scaling (by a factor of approximately 0.44) the voltage to the minus input of the comparator. The IC's VIN+ input is directly connected to the plus input of the comparator. A typical application connects the VIN- input to VCC2 and VIN+ to the reference output for Under-Voltage Detection. The scaling resistors thereby set the threshold to 2.88 V with no additional components required. Hysteresis, of typically 30 mV, can be enabled or disabled via the HYSSEL pin (low is enable), allowing versatility for general purpose applications. The comparator may be used for general purpose applications, if the fixed divider ratio is accounted for. The inputs should not go lower than 1.0 V. The plus input should not exceed VCC2 - 1.0 V and the minus input should not exceed VCC2. The output of the comparator is push-pull, referenced to VLDO_1.85.
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Circuit Features
3.6 OR Gate & Inverter
The IC incorporates a general purpose inverter and OR gate. The Q1_B input is the input to the inverter and one of the OR gate inputs. The S_INV output will be the logical inversion of the input. The S_OR output will be the logical OR of the inverse of Q1_B and Q2. Q2 has an internal pull-down. See Figure 3. A truth table of this function is shown in Table 7:
Table 7. Inverter/OR Logic Truth Table
Q1_B 0 0 1 1 Q2 0 1 0 1 S_OR 1 1 0 1 S_INV 1 1 0 0
1.85 V Q1_B VCC2 Q2 1.0 M S_OR S_INV
Figure 3. Inverter/OR Logic Block Diagram
Both inputs feature voltage robust level shifting and a Vih may range from 1.5 V through VCC2. The inverter output is referenced to VLDO_1.85. The OR gate output is referenced to VCC2.
3.7 Thermal Shutdown
Internal thermal shutdown circuitry is provided to protect the IC and the system in the event that the maximum junction temperature is exceeded. When activated (typical threshold is set at 150C), the three LDO regulators turn off until they are reactivated. This feature is provided to prevent failures from inadvertent overheating. Hysteresis allows stable thermal recovery. Care should be taken in design to ensure that regulator loading and ambient thermal conditions are managed to avoid excessive power dissipation and thermal shutdown in normal operation. PC board layout should include connection to exposed thermal pad on IC and ensure adequate heat dissipation.
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MC13181 Advance Information
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Packaging
4 Packaging
PIN 1 INDEX AREA
0.1 C A 0.1 C
2X
4
2X
M
G 1.0 0.8 1.00 0.75 (0.24) 0.05 0.00 M B (0.5) C DETAIL G
VIEW ROTATED 90 CLOCKWISE
0.1 C 0.05 C 6
4
SEATING PLANE
0.1 C A B
19
2.25 1.95
24
DETAIL M PIN 1 IDENTIFIER EXPOSED DIE ATTACH PAD
0.25
18 1
2.25 1.95 0.1 C A B
13 6
N
12 7
0.5 0.30 0.18 0.1 0.05
20X
24X
0.5 0.3 VIEW M-M (45)
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. CORNER LEADS CAN BE USED FOR THERMAL OR GROUND AND ARE TIED TO THE DIE ATTACH PAD. THESE LEADS ARE NOT INCLUDED IN THE LEAD COUNT. 6. COPLANARITY APPLIES TO LEADS, CORNER LEADS, AND DIE ATTACH PAD. 7. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12.
24X
M M
CAB C
DETAIL T
(90)
(0.25)
2X
0.39 0.31
0.065 0.015
24X
(1.227)
2X
0.1 0.0
DETAIL N
PREFERRED CORNER CONFIGURATION
DETAIL M
PREFERRED PIN 1 BACKSIDE IDENTIFIER
DETAIL T
PREFERRED PIN 1 BACKSIDE IDENTIFIER
4 (45) (90)
DETAIL S
0.60 0.24 (0.4) (0.18) 0.60 0.24 DETAIL N
CORNER CONFIGURATION OPTION 2X
0.39 0.31
0.1 MIN
DETAIL M
PIN 1 BACKSIDE IDENTIFIER OPTION
DETAIL S
PIN 1 BACKSIDE IDENTIFIER OPTION
4
5
Figure 4. Outline Dimensions for QFN-24 (Case 1307-01, Issue B)
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NOTES
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HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. The Bluetooth trademarks are owned by their proprietor and used by Motorola, Inc., under license. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2002
MC13181/D

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